Massive Audio D2500.1 block series Uživatelský manuál

Automatic Projector Tilt CompensationSystemGanesh Ajjanagadde Shantanu Jain James ThomasDecember 10, 2014AbstractWe designed a system that corrects th

memory, and has a single read/write cycle latency, as opposed to the multi-cycle latency of ZBT memory. However, the amount of block memory availableo

529 wire[16:0] vga_out_addr;530 wire[11:0] ntsc_cb_din;531 wire[11:0] ntsc_dout;532 wire[11:0] vga_din;533 wire[11:0] vga_dout;534 wire ntsc_cb_in_wr;

575 cur_y <= cur_y + 1;576 end577 end578579 // instantiate the pixel_map module580 pixel_map pixel_map(.clk(sys_clk),581 .p1_inv(p1_inv),582 .p2_in

621 .a_addr(vga_in_addr),622 .a_din(vga_din),623 .b_clk(vga_clk),624 .b_addr(vga_out_addr),625 .b_dout(vga_dout));626627 /////////////////////////////

667 // allow user to adjust volume668 wire vup,vdown;669 reg old_vup,old_vdown;670 debounce bup(.reset(reset),.clock(clock_27mhz),.noisy(~button3),.cl

713 .audioTrigger(audioTrigger),714715 // AC97 I/O716 .ready(ready),717 .from_ac97_data(from_ac97_data),718 .to_ac97_data(to_ac97_data),719720 // Flas

19 # 5) Reversed disp_data_in and disp_data_out signals, so that "out" is an20 # output of the FPGA, and "in" is an input.21 #22 #

65 NET "ac97_sdata_out" LOC="ac18" | IOSTANDARD=LVDCI_33;66 NET "ac97_sdata_in" LOC="aj24";67 NET "ac97_s

111112 #113 # Video Output114 #115116 NET "tv_out_ycrcb<9>" LOC="p27" | IOSTANDARD=LVDCI_33;117 NET "tv_out_ycrcb<8&

157 NET "tv_in_ycrcb<3>" LOC="r25";158 NET "tv_in_ycrcb<2>" LOC="l30";159 NET "tv_in_ycrcb<

203 NET "ram0_data<12>" LOC="w28" | IOSTANDARD=LVDCI_33 | NODELAY;204 NET "ram0_data<11>" LOC="v28"

was already used for the manual correction system, there was no other way todisplay the percentage of pixels used without showing it on the projected

249 NET "ram1_data<34>" LOC="ah2" | IOSTANDARD=LVDCI_33 | NODELAY;250 NET "ram1_data<33>" LOC="ah1"

295 NET "ram1_address<8>" LOC="ad4" | IOSTANDARD=LVDCI_33;296 NET "ram1_address<7>" LOC="u3" | IOS

341 NET "flash_address<23>" LOC="aj15";342 NET "flash_address<22>" LOC="al25";343 NET "flash_

387 NET "mouse_clock" LOC="ac16";388 NET "mouse_data" LOC="ac15";389 NET "keyboard_clock" LOC="

433 NET "switch<0>" LOC="ak26";434435 #436 # Discrete LEDs437 #438439 NET "led<7>" LOC="ae17" | IO

479 NET "user1<5>" LOC="a9" | IOSTANDARD=LVTTL;480 NET "user1<4>" LOC="a8" | IOSTANDARD=LVTTL;481

525 NET "user3<26>" LOC="f11" | IOSTANDARD=LVTTL;526 NET "user3<25>" LOC="g10" | IOSTANDARD=LVTTL;

571 NET "user4<13>" LOC="e23" | IOSTANDARD=LVTTL;572 NET "user4<12>" LOC="e21" | IOSTANDARD=LVTTL;

617 NET "daughtercard<16>" LOC="G4" | IOSTANDARD=LVTTL;618 NET "daughtercard<15>" LOC="H4" | IOSTA

663664 NET "systemace_ce_b" LOC="E28" | IOSTANDARD=LVTTL;665 NET "systemace_we_b" LOC="P31" | IOSTANDARD=LVTTL

This module first initializes the accelerometer and then reads x and y acceler-ation values from it in a loop. The clock used for accelerometer communi

709710 NET "analyzer3_data<15>" LOC="k24" | IOSTANDARD=LVTTL;711 NET "analyzer3_data<14>" LOC="k25"

6 // Create Date: 16:26:11 11/16/20147 // Design Name:8 // Module Name: acc9 // Project Name:10 // Target Devices:11 // Tool versions:12 // Descriptio

52 output[W-1:0] par);53 reg[W-2:0] par_reg = 0;5455 always @(posedge clk) begin56 par_reg <= {par_reg[W-3:0], ser};57 end5859 assign par = {par_re

98 reg signed [15:0] accum = 0;99 reg [5:0] num_samples = 0;100 reg signed [15:0] data_right_shift;101102 always @(*) begin103 data_right_shift = {dat

144145 reg ncs_reg;146147 wire dev_clk;148 acc_clk ac(.clk(clk), .dev_clk(dev_clk));149150 reg[7:0] par_in;151 reg pts_start;152 par_to_ser pts(.clk(d

190 count <= count + 1;191 end192 end193 X_READ: begin194 if (count == 5’d25) begin195 count <= 0;196 state <= Y_READ;197 end198 else begin19

236 end237 X_READ: begin238 pts_start = (count == 5’d1) ? 1 : 0;239 par_in = (count == 5’d1) ? 8’hF2 : 0; // 1 for R, 1 for MB240 ma_x_in_ready = (cou

16 12’d4: quad_corners = 76’d166903815503556664320;17 12’d5: quad_corners = 76’d166903815503556664320;18 12’d6: quad_corners = 76’d1669038155035566643

62 12’d50: quad_corners = 76’d1342868670646990380595;63 12’d51: quad_corners = 76’d1490297802984343704631;64 12’d52: quad_corners = 76’d15637958438387

108 12’d96: quad_corners = 76’d165458581135586242565;109 12’d97: quad_corners = 76’d165313902172117936646;110 12’d98: quad_corners = 76’d1651692232083

registers is acceptable), and then wait 16 additional cycles for all of our datato be produced on the SDO line. We rotate between a state for reading

154 12’d142: quad_corners = 76’d166903815503556664320;155 12’d143: quad_corners = 76’d166903815503556664320;156 12’d144: quad_corners = 76’d1669038155

200 12’d188: quad_corners = 76’d1563795843838783490619;201 12’d189: quad_corners = 76’d1563795843838783490619;202 12’d190: quad_corners = 76’d15637958

246 12’d234: quad_corners = 76’d606445136314729490457;247 12’d235: quad_corners = 76’d680087433370416177180;248 12’d236: quad_corners = 76’d7537297301

292 12’d280: quad_corners = 76’d166903815503556664320;293 12’d281: quad_corners = 76’d166759137365526861312;294 12’d282: quad_corners = 76’d9268350848

338 12’d326: quad_corners = 76’d166903815503556664320;339 12’d327: quad_corners = 76’d166903815503556664320;340 12’d328: quad_corners = 76’d1669038155

384 12’d372: quad_corners = 76’d1563795843838783490619;385 12’d373: quad_corners = 76’d1563795843838783490619;386 12’d374: quad_corners = 76’d15637958

430 12’d418: quad_corners = 76’d165169223208381195272;431 12’d419: quad_corners = 76’d238811520539482660361;432 12’d420: quad_corners = 76’d2386668415

476 12’d464: quad_corners = 76’d166903815503556664320;477 12’d465: quad_corners = 76’d166903815503556664320;478 12’d466: quad_corners = 76’d1669038155

522 12’d510: quad_corners = 76’d1563795843838783490619;523 12’d511: quad_corners = 76’d1563795843838783490619;524 12’d512: quad_corners = 76’d16690381

568 12’d556: quad_corners = 76’d753729730151224956958;569 12’d557: quad_corners = 76’d827227771281079520801;570 12’d558: quad_corners = 76’d9008700680

5.5 accel lut (Ganesh)The accel lut module provides a look-up table from the accelerometer readingsin two directions to the four corners of the quadri

614 12’d602: quad_corners = 76’d92683508482071876096;615 12’d603: quad_corners = 76’d92538830344042597376;616 12’d604: quad_corners = 76’d923942929435

660 12’d648: quad_corners = 76’d166903815503556664320;661 12’d649: quad_corners = 76’d166903815503556664320;662 12’d650: quad_corners = 76’d1669038155

706 12’d694: quad_corners = 76’d1563795843838783490619;707 12’d695: quad_corners = 76’d1563795843838783490619;708 12’d696: quad_corners = 76’d15637958

752 12’d740: quad_corners = 76’d238666841575745918475;753 12’d741: quad_corners = 76’d312165023443625184781;754 12’d742: quad_corners = 76’d3120203444

798 12’d786: quad_corners = 76’d166903815503556664320;799 12’d787: quad_corners = 76’d166903815503556664320;800 12’d788: quad_corners = 76’d1669038155

844 12’d832: quad_corners = 76’d166903815503556664320;845 12’d833: quad_corners = 76’d166903815503556664320;846 12’d834: quad_corners = 76’d1669038155

890 12’d878: quad_corners = 76’d900870068061619865125;891 12’d879: quad_corners = 76’d1048299200674119531560;892 12’d880: quad_corners = 76’d112194135

936 12’d924: quad_corners = 76’d92394292943501150208;937 12’d925: quad_corners = 76’d92249614805471871489;938 12’d926: quad_corners = 76’d921049366674

982 12’d970: quad_corners = 76’d166903815503556664320;983 12’d971: quad_corners = 76’d166903815503556664320;984 12’d972: quad_corners = 76’d1669038155

1028 12’d1016: quad_corners = 76’d1563795843838783490619;1029 12’d1017: quad_corners = 76’d1563795843838783490619;1030 12’d1018: quad_corners = 76’d15

5.7 bram (Ganesh)The bram module is a very simple true dual port memory module, with exactlyenough storage for a down-sampled frame (320x240) with 12

1074 12’d1062: quad_corners = 76’d312020344479620007951;1075 12’d1063: quad_corners = 76’d385662500798086774801;1076 12’d1064: quad_corners = 76’d4593

1120 12’d1108: quad_corners = 76’d17455098831505222144;1121 12’d1109: quad_corners = 76’d17455098831505222144;1122 12’d1110: quad_corners = 76’d174550

1166 12’d1154: quad_corners = 76’d15724449937206048768;1167 12’d1155: quad_corners = 76’d15724449937206048768;1168 12’d1156: quad_corners = 76’d157244

1212 12’d1200: quad_corners = 76’d1121219941030167831084;1213 12’d1201: quad_corners = 76’d1195006353273661937712;1214 12’d1202: quad_corners = 76’d13

1258 12’d1246: quad_corners = 76’d13702896654474832896;1259 12’d1247: quad_corners = 76’d13558359253933909504;1260 12’d1248: quad_corners = 76’d135577

1304 12’d1292: quad_corners = 76’d12407408074170340352;1305 12’d1293: quad_corners = 76’d12407408074170340352;1306 12’d1294: quad_corners = 76’d124074

1350 12’d1338: quad_corners = 76’d1711513077650142522945;1351 12’d1339: quad_corners = 76’d1711513077650142522945;1352 12’d1340: quad_corners = 76’d17

1396 12’d1384: quad_corners = 76’d233184133442013254670;1397 12’d1385: quad_corners = 76’d307114802161901129234;1398 12’d1386: quad_corners = 76’d3810

1442 12’d1430: quad_corners = 76’d9522993250338384896;1443 12’d1431: quad_corners = 76’d9522993250338384896;1444 12’d1432: quad_corners = 76’d95229932

1488 12’d1476: quad_corners = 76’d8080715469677704704;1489 12’d1477: quad_corners = 76’d8080715469677704704;1490 12’d1478: quad_corners = 76’d80807154

For us, this was of use in generating a clock with a frequency on the orderof a Hz for synchronizing the quadrilateral corner locations and perspectiv

1534 12’d1522: quad_corners = 76’d1562930466363317434938;1535 12’d1523: quad_corners = 76’d1784579343598177498176;1536 12’d1524: quad_corners = 76’d19

1580 12’d1568: quad_corners = 76’d7500454805191828480;1581 12’d1569: quad_corners = 76’d7788262968878473216;1582 12’d1570: quad_corners = 76’d79320966

1626 12’d1614: quad_corners = 76’d5628927685047929344;1627 12’d1615: quad_corners = 76’d5628927685047929344;1628 12’d1616: quad_corners = 76’d56289276

1672 12’d1660: quad_corners = 76’d2153657779787085402696;1673 12’d1661: quad_corners = 76’d2153657779787085402696;1674 12’d1662: quad_corners = 76’d21

1718 12’d1706: quad_corners = 76’d598944964543056221208;1719 12’d1707: quad_corners = 76’d746950980946837671964;1720 12’d1708: quad_corners = 76’d8949

1764 12’d1752: quad_corners = 76’d3465511012983430144;1765 12’d1753: quad_corners = 76’d3609344726351010304;1766 12’d1754: quad_corners = 76’d36089225

1810 12’d1798: quad_corners = 76’d2600116196284883968;1811 12’d1799: quad_corners = 76’d2600116196284883968;1812 12’d1800: quad_corners = 76’d26001161

1856 12’d1844: quad_corners = 76’d2448229086505146811469;1857 12’d1845: quad_corners = 76’d2448229086505146811469;1858 12’d1846: quad_corners = 76’d24

1902 12’d1890: quad_corners = 76’d225110448150078607874;1903 12’d1891: quad_corners = 76’d299185373346091290117;1904 12’d1892: quad_corners = 76’d3732

1948 12’d1936: quad_corners = 76’d74656302857723900416;1949 12’d1937: quad_corners = 76’d74656302857723900416;1950 12’d1938: quad_corners = 76’d746563

turns out that the BRAM design can work equally well with either pior pinvi.However, at this point of the project, we had already started using pinvia

1994 12’d1982: quad_corners = 76’d2742800391296373268561;1995 12’d1983: quad_corners = 76’d2742800391296373268561;1996 12’d1984: quad_corners = 76’d22

2040 12’d2028: quad_corners = 76’d1556444303795027756586;2041 12’d2029: quad_corners = 76’d1704738691587595092526;2042 12’d2030: quad_corners = 76’d18

2086 12’d2074: quad_corners = 76’d442724663065554778624;2087 12’d2075: quad_corners = 76’d442724381591114938368;2088 12’d2076: quad_corners = 76’d4428

2132 12’d2120: quad_corners = 76’d664085591123558202880;2133 12’d2121: quad_corners = 76’d664085591123558202880;2134 12’d2122: quad_corners = 76’d6640

2178 12’d2166: quad_corners = 76’d3184513442750486331479;2179 12’d2167: quad_corners = 76’d3184513442750486331479;2180 12’d2168: quad_corners = 76’d31

2224 12’d2212: quad_corners = 76’d1255963993718749196310;2225 12’d2213: quad_corners = 76’d1330183315578083405337;2226 12’d2214: quad_corners = 76’d14

2270 12’d2258: quad_corners = 76’d1180593578011568963079;2271 12’d2259: quad_corners = 76’d1180593578011568963079;2272 12’d2260: quad_corners = 76’d11

2316 12’d2304: quad_corners = 76’d1475741059602993446412;2317 12’d2305: quad_corners = 76’d1475741059602993446412;2318 12’d2306: quad_corners = 76’d14

2362 12’d2350: quad_corners = 76’d2809958066192020990016;2363 12’d2351: quad_corners = 76’d2958252594996954588740;2364 12’d2352: quad_corners = 76’d31

2408 12’d2396: quad_corners = 76’d1770887837784269979157;2409 12’d2397: quad_corners = 76’d1770887697047318494742;2410 12’d2398: quad_corners = 76’d18

multiplication. Essentially, they correspond to the decrements needed at theend of each horizontal scan line. Note the use of 480, 640 (i.e19204and192

2454 12’d2442: quad_corners = 76’d2139823280280510987800;2455 12’d2443: quad_corners = 76’d2139823280280510987800;2456 12’d2444: quad_corners = 76’d21

2500 12’d2488: quad_corners = 76’d4141438710486757336673;2501 12’d2489: quad_corners = 76’d4141438710486757336673;2502 12’d2490: quad_corners = 76’d41

2546 12’d2534: quad_corners = 76’d2878556890213738413618;2547 12’d2535: quad_corners = 76’d2878989236053112323636;2548 12’d2536: quad_corners = 76’d29

2592 12’d2580: quad_corners = 76’d2877692617715208748581;2593 12’d2581: quad_corners = 76’d2877692617715208748581;2594 12’d2582: quad_corners = 76’d28

2638 12’d2626: quad_corners = 76’d3246627356526423899692;2639 12’d2627: quad_corners = 76’d3246627356526423899692;2640 12’d2628: quad_corners = 76’d32

2684 12’d2672: quad_corners = 76’d4358620011940779194456;2685 12’d2673: quad_corners = 76’d4432983590000555521628;2686 12’d2674: quad_corners = 76’d45

2730 12’d2718: quad_corners = 76’d3689348931723649154615;2731 12’d2719: quad_corners = 76’d3689348931724186025528;2732 12’d2720: quad_corners = 76’d36

2776 12’d2764: quad_corners = 76’d4132070927201141063228;2777 12’d2765: quad_corners = 76’d4132070927201141063228;2778 12’d2766: quad_corners = 76’d41

2822 12’d2810: quad_corners = 76’d5245217772407034278508;2823 12’d2811: quad_corners = 76’d5245217772407034278508;2824 12’d2812: quad_corners = 76’d52

2868 12’d2856: quad_corners = 76’d4797162380265072164435;2869 12’d2857: quad_corners = 76’d4797450610916370218581;2870 12’d2858: quad_corners = 76’d48

width of 32 bits, which is insufficient for our needs. Furthermore, they discour-age creation of pipe-lined dividers of greater width due to the high ar

2914 12’d2902: quad_corners = 76’d5091301614633037921870;2915 12’d2903: quad_corners = 76’d5091301614633037921870;2916 12’d2904: quad_corners = 76’d50

2960 12’d2948: quad_corners = 76’d5607810446221392019032;2961 12’d2949: quad_corners = 76’d5607810446221392019032;2962 12’d2950: quad_corners = 76’d56

3006 12’d2994: quad_corners = 76’d5980349620554196381807;3007 12’d2995: quad_corners = 76’d5980638132680202710641;3008 12’d2996: quad_corners = 76’d60

3052 12’d3040: quad_corners = 76’d6050532162156376161890;3053 12’d3041: quad_corners = 76’d6050676277619598360163;3054 12’d3042: quad_corners = 76’d60

3098 12’d3086: quad_corners = 76’d6715336083845781190252;3099 12’d3087: quad_corners = 76’d6715336083845781190252;3100 12’d3088: quad_corners = 76’d67

3144 12’d3132: quad_corners = 76’d6569781719993962783863;3145 12’d3133: quad_corners = 76’d6569781719993962783863;3146 12’d3134: quad_corners = 76’d65

3190 12’d3178: quad_corners = 76’d7010772642168345260662;3191 12’d3179: quad_corners = 76’d7010916898094177907318;3192 12’d3180: quad_corners = 76’d70

3236 12’d3224: quad_corners = 76’d7971300364638276086403;3237 12’d3225: quad_corners = 76’d7897369273430777850498;3238 12’d3226: quad_corners = 76’d78

3282 12’d3270: quad_corners = 76’d8562461285587240673934;3283 12’d3271: quad_corners = 76’d8562461285587240673934;3284 12’d3272: quad_corners = 76’d85

3328 12’d3316: quad_corners = 76’d7526419313699181088895;3329 12’d3317: quad_corners = 76’d7526419313699181088895;3330 12’d3318: quad_corners = 76’d75

AcknowledgmentsFirst and foremost, we would like to thank our 6.111 instructor Gim Hom for histremendous patience, experience, and intuition regarding

than the NTSC data was coming to us (the tv in line clock1 rate). This wascausing some setup times at the BRAM to be violated when clocks were out ofp

3374 12’d3362: quad_corners = 76’d8930675730211157107860;3375 12’d3363: quad_corners = 76’d8856744779740878791827;3376 12’d3364: quad_corners = 76’d87

3420 12’d3408: quad_corners = 76’d9227553297744240892571;3421 12’d3409: quad_corners = 76’d9227553297744240892571;3422 12’d3410: quad_corners = 76’d92

3466 12’d3454: quad_corners = 76’d7821423522051142764673;3467 12’d3455: quad_corners = 76’d7821423522051142764673;3468 12’d3456: quad_corners = 76’d92

3512 12’d3500: quad_corners = 76’d8412438359690244316298;3513 12’d3501: quad_corners = 76’d8338507408944551221897;3514 12’d3502: quad_corners = 76’d82

3558 12’d3546: quad_corners = 76’d9227264926906554048154;3559 12’d3547: quad_corners = 76’d9153333694961567457433;3560 12’d3548: quad_corners = 76’d91

3604 12’d3592: quad_corners = 76’d9227553297744240892571;3605 12’d3593: quad_corners = 76’d9227553297744240892571;3606 12’d3594: quad_corners = 76’d92

3650 12’d3638: quad_corners = 76’d7821423522051142764673;3651 12’d3639: quad_corners = 76’d7821423522051142764673;3652 12’d3640: quad_corners = 76’d78

3696 12’d3684: quad_corners = 76’d8782669573069889922194;3697 12’d3685: quad_corners = 76’d8782525458156960933009;3698 12’d3686: quad_corners = 76’d87

3742 12’d3730: quad_corners = 76’d9227553297744240892571;3743 12’d3731: quad_corners = 76’d9227553297744240892571;3744 12’d3732: quad_corners = 76’d92

3788 12’d3776: quad_corners = 76’d9227553297744240892571;3789 12’d3777: quad_corners = 76’d9227553297744240892571;3790 12’d3778: quad_corners = 76’d92

deleting its contents, which the labkit automatically does when it is poweredon, the module also has a “reset disable” switch.When in “write mode”, th

3834 12’d3822: quad_corners = 76’d8264432483748538538120;3835 12’d3823: quad_corners = 76’d8190501533277723350663;3836 12’d3824: quad_corners = 76’d81

3880 12’d3868: quad_corners = 76’d9153045464585685229720;3881 12’d3869: quad_corners = 76’d9079114373378186470040;3882 12’d3870: quad_corners = 76’d90

3926 12’d3914: quad_corners = 76’d9227553297744240892571;3927 12’d3915: quad_corners = 76’d9227553297744240892571;3928 12’d3916: quad_corners = 76’d92

3972 12’d3960: quad_corners = 76’d7821423522051142764673;3973 12’d3961: quad_corners = 76’d7821423522051142764673;3974 12’d3962: quad_corners = 76’d78

4018 12’d4006: quad_corners = 76’d8708594507411536274576;4019 12’d4007: quad_corners = 76’d8634663416203500643471;4020 12’d4008: quad_corners = 76’d86

4064 12’d4052: quad_corners = 76’d9227553297744240892571;4065 12’d4053: quad_corners = 76’d9227553297744240892571;4066 12’d4054: quad_corners = 76’d92

4110 endmoduleA.3.3 accel lut.jl1 #=2 This script generates an accel_lut.v file.3 accel_lut.v contains a verilog implementation of a lookup table,4 wh

43 function parse_data(path)44 raw_data = read_file(path)45 num_samples = size(raw_data)[1]46 x_accel = zeros(Int64, num_samples)47 y_accel = zeros(In

89 x[i+1] = i >> 690 y[i+1] = i & ((1 << 6) - 1)91 end9293 # do the spline interpolation94 # we do linear fits for now95 # as we add m

135 for i=1:2^12136 quad_corners[i] = y4_interp[i] + (x4_interp[i] << 9) + (y3_interp[i] << 19) + (x3_interp[i] << 28)137 quad_corne

ity to the user than the seemingly-opaque efficient algorithms, at the expenseof utilizing more of the scarce look-up tables on the hardware.6 Final Pro

10 18,20, 0,33, 3b,1df, 27f,1a5, 249,011 10,20, 0,07e, 60,1df, 27f,158, 21b,012 20,18, 8,0, 16,1df, 26a,1df, 27f,0A.3.5 pixels kept.v1 ///////////////

41 assign sy4 = {1’b0, y4};4243 // difference terms44 assign d_x1_x3 = sx1 - sx3;45 assign d_x2_x4 = sx2 - sx4;46 assign d_y1_y3 = sy1 - sy3;47 assign

9 // unnecessary Coregen usage10 //11 // credits: http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/12 ///////////////////////////////////////

16 assign addr = (vcount[9:1] << 8) + (vcount[9:1] << 6) + (hcount >> 1);17 endmoduleA.3.8 slow clk.v1 /////////////////////////////

13 input up,14 input down,15 input left,16 input right,17 input override,18 input[1:0] switch,19 input[9:0] x1_raw,20 input[8:0] y1_raw,21 input[9:0]

59 2’b10: begin60 display_x <= x3;61 display_y <= y3;62 end63 2’b11: begin64 display_x <= x4;65 display_y <= y4;66 end67 endcase68 end6970

105 else if (left) begin106 x2 <= (x2 >= XSPEED) ? (x2 - XSPEED) : x2;107 end108 else if (right) begin109 x2 <= (x2 <= SCR_WIDTH-XSPEED) ?

151 cur_state <= ~OVERRIDE;152 end153 end154155 endmoduleA.3.10 perspective params.v1 /////////////////////////////////////////////////////////////

39 //40 // Future improvements:41 // 1)42 // This module uses over 120 out of 144 available 18x1843 // multipliers!!!44 // By reducing bitwidths and a

85 wire signed[9:0] sy1, sy2, sy3, sy4;86 assign sx1 = {1’b0, x1};87 assign sx2 = {1’b0, x2};88 assign sx3 = {1’b0, x3};89 assign sx4 = {1’b0, x4};90

Figure 6: User InterfaceWhen pressed, button 0 triggers the audio system, which announces thepercentage of screen pixels currently used for the correc

131 wire signed[25:0] denom_15;132 wire signed[32:0] p9;133 wire signed[32:0] x1_denom;134 wire signed[36:0] x1_denom_15;135 wire signed[43:0] p3;136

177 assign p4 = y4_p7 + d_y4_y1_denom_scale;178 assign p5 = y2_p8 - d_y1_y2_denom_scale;179180 // 36, 36, 44, 35, 35, 43, 24, 24, 33181 // computation

223 end224225 endmoduleA.3.11 pixel map.v1 ‘default_nettype none2 ////////////////////////////////////////////////////////////////////////////////////

41 // internal registers for numerator and denominator computation42 // see perspective_params.v for the equations43 reg signed[78:0] num_x = 0;44 reg

87 .addr(ntsc_out_addr));8889 parameter NEXT_PIXEL_ST = 2’b00;90 parameter WAIT_FOR_DIV_ST = 2’b01;91 parameter WAIT_FOR_MEM_ST = 2’b10;92 parameter B

133 pixel_out <= BLACK;134 vga_in_wr <= 1;135 cur_state <= NEXT_PIXEL_ST;136 end137 else begin138 pixel_out <= pixel_in;139 vga_in_wr <

31 output wire flash_oe_b,32 output wire flash_we_b,33 output wire flash_reset_b,34 output wire flash_byte_b,35 input wire flash_sts,36 output wire bu

7778 reg writemode = 0; // 1=write mode; 0=read mode79 reg [15:0] wdata = 0; // writeData80 reg dowrite = 0; // 1=new data, write it81 reg [22:0] radd

123124 // Interface125 .out(out[7:0]),126 .newout(newout),127 .hold(hold)128 );129130 wire [3:0] hundreds;131 wire [3:0] tens;132 wire [3:0] ones;1331

169 doread <= 1’b0;170 //dowrite <= 1’b0; // only write on new data // WATCH OUT!!171 if (newout) begin172 bytesRxed <= bytesRxed + 1;173 wda

trigger an incremental build that can complete on the order of seconds, synthesisof FPGA hardware is a lengthy process, taking on the order of minutes

215 5: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, FIVE_INDEX};216 6: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, SIX_INDEX};217 7:

261 else begin262 raddr <= playbackSeq[22:0] * TRACK_LENGTH;263 trackEndAddr <= playbackSeq[22:0] * TRACK_LENGTH + TRACK_LENGTH;264 end265 end26

15 2: begin ones <= 2; tens <= 0; end16 3: begin ones <= 3; tens <= 0; end17 4: begin ones <= 4; tens <= 0; end18 5: begin ones <

61 48: begin ones <= 8; tens <= 4; end62 49: begin ones <= 9; tens <= 4; end63 50: begin ones <= 0; tens <= 5; end64 51: begin ones

107 94: begin ones <= 4; tens <= 9; end108 95: begin ones <= 5; tens <= 9; end109 96: begin ones <= 6; tens <= 9; end110 97: begin o

16 end17 else if (counter == (fastMode ? 3:Hz)) begin18 oneHertz_enable <= 1’b1;19 counter <= 25’b0;20 end21 else begin22 counter <= counter

track of the current bit was only 6 bits wide, which supports only operand bitwidths up to 63. We extended the width of this counter to 7 bits to solv

It did not take us too long to realize the mistake in the implementation, andlooking back we do not see any other way of correcting the mistake.As des

from 100 to get the correct value. The playback of the percentage was oftenincorrect for some reason (never identified). Initially, we were keen on fixi

• Store the look-up table in a larger memory, e.g ZBT.• A more scalable approach is to start doing interpolation in the hardwareitself. This will requ

issues as early as possible, with a consistent time commitment every week.Second, we spent a lot of time doing software simulations/verifications befor

Contents1 Introduction 52 Previous Work 63 Module Architecture 63.1 Accelerometer interface . . . . . . . . . . . . . . . . . . . . . . . 73.2 Perspec

A Source CodeSource code for the project may be obtained on GitHub: https://github.com/gajjanag/6111_Project. For completeness, we include all source

A.1.2 delay.v1 ‘timescale 1ns / 1ps2 //////////////////////////////////////////////////////////////////////////////////3 // Company:4 // Engineer:5 //

10 //11 // 24-Sep-05 Ike: updated to use new reset-once state machine, remove clear12 // 28-Nov-06 CJT: fixed race condition between CE and RS (thanks

56 end57 else58 count = count+1;59 end6061 always @(posedge clock_27mhz)62 if (reset)63 reset_count <= 100;64 else65 reset_count <= (reset_count

102 dot_index <= 0;103 state <= state+1;104 end105106 8’h01:107 begin108 // End reset109 disp_reset_b <= 1’b1;110 state <= state+1;111 end

148 disp_ce_b <= 1’b1;149 dot_index <= 39; // init for single char150 char_index <= 15; // start with MS char151 state <= state+1;152 disp

194 always @(nibble)195 case (nibble)196 4’h0: dots <= 40’b00111110_01010001_01001001_01000101_00111110;197 4’h1: dots <= 40’b00000000_01000010_

2324 // horizontal: 800 pixels total25 // display 640 pixels per line26 reg hblank,vblank;27 wire hsyncon,hsyncoff,hreset,hblankon;28 assign hblankon

10 module divider #(parameter WIDTH = 8)11 (input clk, sign, start,12 input [WIDTH-1:0] dividend,13 input [WIDTH-1:0] divider,14 output reg [WIDTH-1:0

56 end57 quotient = (!negative_output) ?58 quotient_temp :59 ~quotient_temp + 1’b1;60 divider_copy = divider_copy >> 1;61 bit = bit - 1’b1;62 en

8 Future Work 279 Conclusion 28A Source Code 30A.1 Staff Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30A.1.1 debounce.v . . . . .

35 begin36 const1 = 10’b 0100101010; //1.164 = 01.0010101037 const2 = 10’b 0110011000; //1.596 = 01.1001100038 const3 = 10’b 0011010000; //0.813 = 00.

81 /*always @ (posedge clk or posedge rst)82 if (rst)83 begin84 R_int <= 0; G_int <= 0; B_int <= 0;85 end86 else87 begin88 X_int <= (const

24 reg old_frame; // frames are even / odd interlaced25 reg even_odd; // decode interlaced frame to this wire2627 wire frame = fvh[2];28 wire frame_ed

7071 // compute address to store data in72 wire [9:0] y_addr = {y[1][8:0], eo[1]};73 wire [9:0] x_addr = x[1];7475 wire [7:0] R, G, B;76 ycrcb2rgb con

19 // that are encoded within the stream, in YCrCb format.2021 // Make sure that the adv7185 is set to run in 16-bit LLC2 mode.2223 module ntsc_decode

65 // in the sequence of pixels, it is looking.6667 // Once we determine where to start, the FSM goes through a normal68 // sequence of SAV process_YC

111 SAV_f2_cb0: current_state <= (tv_in_ycrcb == 10’h3ff) ? SYNC_1 : SAV_f2_y0;112 SAV_f2_y0: current_state <= (tv_in_ycrcb == 10’h3ff) ? SYNC_1

157 y <= y_enable ? tv_in_ycrcb : y;158 cr <= cr_enable ? tv_in_ycrcb : cr;159 cb <= cb_enable ? tv_in_ycrcb : cb;160 f <= (current_state

203 ///////////////////////////////////////////////////////////////////////////////204 // Register 1205 //////////////////////////////////////////////

249 ‘define ADV7185_REGISTER_2 {3’b000, ‘CORING, ‘Y_PEAKING_FILTER}250251 ////////////////////////////////////////////////////////////////////////////

1 IntroductionDue to the advances in semiconductor technology, today’s display projectorscan incorporate fairly sophisticated digital processing algor

295296 ‘define GENERAL_PURPOSE_OUTPUTS 4’b0000297 ‘define GPO_0_1_ENABLE 1’b0298 // 0: General purpose outputs 0 and 1 tristated299 // 1: General purp

341342 ‘define INPUT_SATURATION_ADJUST 8’h8C343344 ‘define ADV7185_REGISTER_9 {‘INPUT_SATURATION_ADJUST}345346 ///////////////////////////////////////

387388 ///////////////////////////////////////////////////////////////////////////////389 // Register E390 ///////////////////////////////////////////

433 ‘define ADV7185_REGISTER_F {‘RESET_CHIP, ‘TIMING_REACQUIRE, ‘POWER_DOWN_CHIP, ‘POWER_DOWN_LLC_GENERATOR, ‘POWER_DOWN_REFERENCE, ‘POWER_DOWN_SOURCE

479 ‘define ADV7185_REGISTER_24 8’h1F480 ‘define ADV7185_REGISTER_25 8’h07481 ‘define ADV7185_REGISTER_26 8’hC2482 ‘define ADV7185_REGISTER_27 8’h5848

525 $display(" Register 3: 0x%X", ‘ADV7185_REGISTER_3);526 $display(" Register 4: 0x%X", ‘ADV7185_REGISTER_4);527 $display("

571 assign reset_slow = reset_count != 0;572573 //574 // I2C driver575 //576577 reg load;578 reg [7:0] data;579 wire ack, idle;580581 i2c i2c(.reset(r

617 state <= state+1;618 end619 8’h03:620 begin621 // Send ADV7185 address622 data <= 8’h8A;623 load <= 1’b1;624 if (ack)625 state <= stat

663 begin664 // Write to register 4665 data <= ‘ADV7185_REGISTER_4;666 if (ack)667 state <= state+1;668 end669 8’h0A:670 begin671 // Write to re

709 end710 8’h10:711 begin712 // Write to register B713 data <= ‘ADV7185_REGISTER_B;714 if (ack)715 state <= state+1;716 end717 8’h11:718 begin7

Finally, we also provide a useful voice output for the percentage of pixels keptafter the perspective transformation (this is a lossy transformation i

755 data <= 8’h8A;756 load <= 1’b1;757 if (ack)758 state <= state+1;759 end760 8’h17:761 begin762 data <= 8’h33;763 if (ack)764 state <

801 if (ack)802 state <= state+1;803 end804 8’h1E:805 begin806 data <= 8’hFF;807 if (ack)808 state <= state+1;809 end810 8’h1F:811 begin812 l

847 // i2c module for use with the ADV7185848849 module i2c (reset, clock4x, data, load, idle, ack, scl, sda);850851 input reset;852 input clock4x;853

893 idle <= 1’b0;894 sdai <= 1’b0;895 state <= state+1;896 end897 8’h02:898 begin899 scl <= 1’b0;900 state <= state+1;901 end902 8’h03:

939 state <= state+1;940 end941 8’h0B:942 begin943 sdai <= ldata[5];944 state <= state+1;945 end946 8’h0C:947 begin948 scl <= 1’b1;949 sta

985 begin986 scl <= 1’b1;987 state <= state+1;988 end989 8’h15:990 begin991 state <= state+1;992 end993 8’h16:994 begin995 scl <= 1’b0;996

1031 8’h1E:1032 begin1033 scl <= 1’b0;1034 state <= state+1;1035 end1036 8’h1F:1037 begin1038 sdai <= ldata[0];1039 state <= state+1;1040

1077 else1078 state <= state+1;1079 end1080 8’h27:1081 begin1082 sdai <= 1’b0;1083 state <= state+1;1084 end1085 8’h28:1086 begin1087 scl <

2122 reg [1:0] lop;23 reg [15:0] rdata;24 reg busy;25 reg [15:0] flash_wdata;26 reg flash_ddata;27 reg [23:0] flash_address;28 reg flash_oe_b, flash_w

67 flash_ddata <= 0;68 flash_wdata <= wdata;69 lop <= op;70 if (op != ‘FLASHOP_IDLE)71 begin72 busy <= 1;73 state <= state+1;74 end75 e

Figure 2: Block DiagramOur keystone correction system can be divided into roughly four functionalcomponents:1. Accelerometer interface2. Perspective t

113 busy <= 1;114 state <= state+1;115 end116117 endmoduleA.1.10 flash manager.v1 //manages all the stuff needed to read and write to the flash R

3940 wire flash_busy; //except these, which are internal to the interface41 wire[15:0] fwdata;42 wire[15:0] frdata;43 wire[22:0] address;44 wire [1:0]

85 busy <= 0;86 if(writemode)87 begin88 busy <= 1;89 state <= MEM_INIT;90 end91 else92 begin93 busy <= 1;94 state <= READ_READY;95 end9

131 busy <= 0;132 state <= WRITE_READY;133 end134 else135 mode <= MODE_IDLE;136137 READ_READY://5 //ready to read data138 if(doread)139 begin

12 ‘define STATUS_WRITE_ERROR 4’hB13 ‘define STATUS_READ_WRONG_DATA 4’hC1415 ‘define NUM_BLOCKS 12816 ‘define BLOCK_SIZE 64*102417 ‘define LAST_BLOCK_

5859 parameter MAX_ADDRESS = 23’h200000;6061 parameter HOME = 8’h12;626364 always @(posedge clock)65 if (reset)66 begin67 state <= HOME;68 status &

104 //////////////////////////////////////////////////////////////////////105 8’h00:106 begin107 // Issue "read id codes" command108 status

150 fwdata <= 16’h60;151 fop <= ‘FLASHOP_WRITE;152 state <= state+1;153 end154155 8’h05:156 begin157 // Issue "confirm clear lock bits&q

196 state <= state+1;197 end198199 8’h09:200 begin201 fwdata <= 16’hD0; // Issue "confirm erase" command202 fop <= ‘FLASHOP_WRITE;2

242 8’h0D:243 begin244 fwdata <= data_to_store; // Finish write245 fop <= ‘FLASHOP_WRITE;246 state <= state+1;247 end248 8’h0E:249 begin250 /

uses the par to ser and ser to par modules to initialize the accelerometer andfetch x and y acceleration readings from it in a loop, averaging them us

288 fop <= ‘FLASHOP_READ;289 state <= HOME;290 end291292 default:293 begin294 status <= ‘STATUS_BAD_MANUFACTURER;295 faddress <= 0;296 sta

334 nib2char(faddress[15:12]),335 nib2char(faddress[11:8]),336 nib2char(faddress[7:4]),337 nib2char(faddress[3:0])};338339 always @(status or address_

380 40’b00000000_00000000_00000000_00000000_00000000, //381 address_dots};382 ‘STATUS_ERASING:383 dots <= {40’b01111111_01001001_01001001_01001001_

426 40’b00100110_01001001_01001001_01001001_00110010, // S427 40’b00100110_01001001_01001001_01001001_00110010, // S428 40’b01111111_01001001_01001001

472 40’b01111111_00001000_00010100_00100010_01000001, // K473 40’b00100110_01001001_01001001_01001001_00110010, // S474 40’b00000000_00000000_00000000

518 endmoduleA.1.12 usb input.v1 //reads data and puts it on out2 module usb_input(clk,reset,data,rd,rxf,out,newout,hold,state);3 input clk, reset; //

43 rd <= 1; //we can’t read data44 state <= WAIT;45 end46 else47 if(~hold)48 begin49 newout <= 0;50 case(state)51 WAIT:52 if(~rxf) //if rxf i

89 newout <= 1; //let folks know we’ve got new data90 end9192 DATA_LEAVING: //wait a cycle to clear the data to make sure we latch onto it correctl

1213 Script runs through a coe file (basically row after row of 8 bit values) and14 sends line by line.15 ’’’1617 ser = serial.Serial(port=’/dev/tty.u

23 // CHANGES FOR BOARD REVISION 00324 //25 // 1) Combined flash chip enables into a single signal, flash_ce_b.26 //27 // CHANGES FOR BOARD REVISION 0

low-level details of working with the flash. When the audio is triggered via anexternal button input, audioManager handles queuing up the appropriate s

69 vga_out_red, vga_out_green, vga_out_blue, vga_out_sync_b,70 vga_out_blank_b, vga_out_pixel_clock, vga_out_hsync,71 vga_out_vsync,7273 tv_out_ycrcb,

115116 analyzer1_data, analyzer1_clock,117 analyzer2_data, analyzer2_clock,118 analyzer3_data, analyzer3_clock,119 analyzer4_data, analyzer4_clock);12

161 input mouse_clock, mouse_data, keyboard_clock, keyboard_data;162163 input clock_27mhz, clock1, clock2;164165 output disp_blank, disp_clock, disp_r

207 assign tv_out_hsync_b = 1’b1;208 assign tv_out_vsync_b = 1’b1;209 assign tv_out_blank_b = 1’b1;210 assign tv_out_subcar_reset = 1’b0;211212 // Vid

253 // // flash_sts is an input254255 // RS-232 Interface256 assign rs232_txd = 1’b1;257 assign rs232_rts = 1’b1;258 // rs232_rxd and rs232_cts are in

299 //300 // A shift register primitive is used to generate an active-high reset301 // signal that remains high for 16 clock cycles after configuratio

345 ///////////////////////////////////////////////////////////////////////////////////////////////////346 wire btn_up_clean, btn_down_clean, btn_left

391 ///////////////////////////////////////////////////////////////////////////////////////////////////392 wire acc_ready;393 wire signed [15:0] acc_x

437 assign y1_raw = quad_corners[65:57];438 assign x1_raw = quad_corners[75:66];439 move_cursor move_cursor(.clk(vsync),440 .up(btn_up_sw & ~old_b

483 ///////////////////////////////////////////////////////////////////////////////////////////////////484 wire signed[67:0] p1_inv;485 wire signed[68